1. Field of the Invention
The present invention relates to telecommunications. More particularly, the present invention relates to the passing of high speed Asynchronous Transfer Mode (ATM) data over a standardized Universal Test and Operations Physical Interface for ATM (UTOPIA) bus.
2. State of the Art
Perhaps the most awaited, and now fastest growing technology in the field of telecommunications in the last decade is known as ATM (Asynchronous Transfer Mode) technology. ATM is providing a mechanism for removing performance limitations of local area networks (LANs) and wide area networks (WANs) and providing data transfers at a speed on the order of gigabits/second. Within the ATM technology, a commonly used interface specification between chips on a board for passing ATM cells is the UTOPIA (Universal Test & Operations PHY Interface for ATM) interface. The UTOPIA interface is specified in ATM Forum standard specifications: af-phy-0017.000 (UTOPIA Level 1, Version 2.01 Mar. 21, 1994); af_phy—0039.000 (UTOPIA Level 2, Version 1, June 1995); and af-phy-00136.000 (UTOPIA 3 Physical Layer Interface November 1999) which are hereby incorporated by reference herein in their entireties.
As mentioned above, the UTOPIA interface is defined by the ATM Forum to allow a common interface between the Physical Layer (PHY) and ATM layer in an ATM system. Currently, four levels of UTOPIA interfaces are defined by the ATM Forum to support a wide range of speed and media types from low speed xDSL to high speed OC-192. A typical application of the UTOPIA interface is supporting the connection between an ATM network processor and various PHY devices such as a DSL chip set and/or a SONET framer. UTOPIA may also used as the interface between a switch fabric and an ATM network processor.
UTOPIA supports three operation modes: single PHY operation mode, Multiple PHY (MPHY) with Direct Status Indication operation mode and MPHY with Multiplexed Status Polling operation mode. In the single PHY mode, the UTOPIA interface includes a data bus and a control bus. The operation of UTOPIA in the single PHY mode is relatively simple and straightforward. In MPHY operation mode, the UTOPIA interface includes a data bus, a control bus and an address bus.
The MPHY UTOPIA transmit interface includes the following signals: transmit data (TxData), transmit address (TxAddr), and the transmit control signals including transmit cell available (TxClav), transmit enable (TxEnb*) and transmit start of cell (TxSOC). The receive interface includes the following signals: receive data (RxData), receive address (RxAddr), and the receive control signals including receive cell available (RxClav), receive enable (RxEnb*) and receive start of cell (RxSOC). A MPHY device may consist of multiple logical PHY ports. Each PHY port has a one-to-one correspondence with a PHY Port address that is related to a UTOPIA address and Clav (Cell buffer available) signal.
Prior art FIG. 1 illustrates an example of a UTOPIA Level 2 interface supporting MPHY with Multiplexed Status Polling operation. Multiplexed Status Polling is mainly used in actual applications. As shown in FIG. 1, a transmit clock signal (TxClk) is used to clock control signals and data signals in the transmit direction (from the ATM device to the PHY devices). The TxData[15:0] signal is a 16-bit UTOPIA transmit data bus. The assertion of TxEnb* is coincident with the start of the cell transfer. TxSOC is used to indicate the start of cell position. TxClav is used to indicate that the PHY layer device is ready to receive a cell from the ATM layer device. TxAddr[4:0] is the UTOPIA address and is used to poll and select the appropriate MPHY device.
At the UTOPIA transmit interface, the ATM layer device polls the TxClav status of a PHY layer device by placing a specified address on the TxAddr bus for one clock cycle. The PHY layer device which is associated with the address on the TxAddr bus drives TxClav high (or low) during the next clock cycle during which the ATM device places a null address (1F) on the TxAddr bus. The ATM layer device checks TxClav at a certain time after it issues TxAddr. Based on polled TxClav information, the ATM layer device can select a PHY device and transfer data to this PHY device by driving TxEnb*, TxAddr, and TxSOC signals.
Similarly, RxClk is the receive clock signal that is used to clock control signals and data in the receive direction (from the PHY device to the ATM device). RxData[15:0] is a 16-bit UTOPIA Receive bus. The assertion of RxEnb* is coincident with the start of the cell transfer. RxSOC is used to indicate the start of cell position. RxClav is used to indicate that the PHY layer device is ready to Receive a cell from the ATM layer device. RxAddr[4:0] is the UTOPIA address of the PHY device and is used by the ATM device to poll and select the appropriate PHY device in the receive direction.
At the UTOPIA receive interface, the ATM layer device polls the RxClav status of a PHY layer device by placing a specified address on RxAddr bus for one clock cycle. The PHY layer device which is associated with the address on the RxAddr bus drives RxClav high (or low) during the next clock cycle during which the ATM device places a null address (1F) on the RxAddr bus. The ATM layer device checks RxClav at a certain time after it issues RxAddr. Based on polled RxClav information, the ATM layer device can select a PHY device and receive data from this PHY device by driving RxEnb* and RxAddr signals.
Certain timing requirements must be met for the Multiplexed Status Polling operation of the UTOPIA interface so that the ATM layer device can correctly detect Clav (Cell buffer available) information. FIG. 2 depicts the timing requirement for UTOPIA level 2 address polling. An ATM device starts driving UTOPIA address N at time t1. The PHY device having address N responds to address polling by driving the Clav signal high (or low) at time t2. The Clav becomes valid for the ATM device at time t3 (after transmission delay) as illustrated by the last line of the timing diagram. The ATM device checks the Clav signal at time t4 in order to accommodate a certain amount of transmission delay. To guarantee correct operation, the Clav signal must be valid before it is checked by ATM device, i.e. at some t3<t4. This is a necessary timing requirement for the UTOPIA interface.
From the foregoing, it will be appreciated that UTOPIA allows many PHY devices to communicate with one ATM layer device. Access to the UTOPIA bus is controlled by the ATM layer device which is considered the bus “master”. The PHY devices are thus considered bus “slaves”. It would be desirable, however, to allow more than one ATM layer device to be coupled to the same UTOPIA bus so as to provide either redundancy or load sharing.